To reduce power consumption, it is conventional to power down or turn off some of the system's integrated circuits in certain modes of operation. An active integrated circuit may then not be aware as to whether other integrated circuits in the same system are powered on or off. If the active integrated circuit attempts to communicate with a powered-off integrated circuit by driving it with an input signal, the resulting “back-power” applied to the inactive integrated circuit may cause the dissipation of relatively large amounts of current. In addition, the back-power may force the inactive integrated circuit into undesirable modes of operation when the inactive integrated circuit subsequently transitions into normal operation, leading to unexpected behaviors or glitches.
The back-power problem may be better appreciated with reference to an example system 100 as shown in FIG. 1. A first integrated circuit 105 is active so that its output buffer A1 continues to drive a binary high (a power supply voltage) signal to an inactive integrated circuit 110. The receiving pin RX on inactive integrated circuit 110 couples to a receive buffer (not illustrated) and also to an output buffer formed by a stack of a PMOS transistor MP and an NMOS transistor MN. During normal operation of integrated circuit 110, a pre-driver circuit drives the gates of transistors MP and MN to produce a desired output signal. However, during the inactive mode in which integrated circuit 110 is powered down, both gates of transistors MP and MN discharge to ground. As is conventional, integrated circuit 110 includes an electrostatic discharge (ESD) protection diode D1 that couples between the RX pin and a power supply rail PX. Another ESD protection diode D2 couples between ground and the RX pin. Since the PX rail is powered down when integrated circuit 110 is inactive, ESD diode D1 becomes forward biased such that an undesirable leakage current will flow from integrated circuit 105 into the PX rail. In turn, the PN junction between the drain for transistor MP and its n-well becomes forward biased and is represented by a parasitic diode D3. The resulting back-power current through ESD diode D1 and parasitic diode D3 into the PX rail and the n-well is represented in FIG. 1 as a back-power current path 115. This back-power current conduction not only wastes power but may also result in glitches or other undesirable states for integrated circuit 110 when it again is powered and attempts to resume normal operation.
Accordingly, there is a need in the art for low-power and compact solutions to the back-power problem.